The present invention relates to a video system pulse generating circuit. More particularly, it relates to a generating circuit of a video system pulse which is a clock pulse as a reference synchronized with an input image input into a signal control section when displaying an image picked up with a camera or the like in a monitor TV or the like.
Herein, the video system pulse (hereinafter referred to as "system pulse") refers to a clock pulse as a reference necessary for driving a display for showing a video signal.
In a video processing system for displaying a video signal input from an image pickup device 11 such as a CCD camera in a display device such as a television monitor, the system pulse that can be provided to a CRTC which is a necessary control unit for controlling signal from a camera or the like or a monitor TV display control is generated conventionally in a circuit as shown in FIG. 3. First, the video signal picked up with the CCD camera 11 is input into a video synchronizing signal separation genarating circuit 10, and a horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) are output as video synchronizing signals. The horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) are input into a CRT display control IC (hereinafter referred to as "CRTC") 14, and the horizontal synchronizing signal (HD) is also used for resetting a dividing circuit 12. The system pulse necessary for operating the CRTC is reset by the horizontal synchronizing signal and is matched in phase as the clock pulse from a quartz oscillator 13 and is set to the same frequency as the synchronizing signal of the video signal from the dividing circuit 12, and the system pulse synchronized with the video synchronizing signal is provided for the CRTC for display control of monitor TV.
The CRTC is an IC or an arbitrarily designed circuit for performing necessary control such as a control of signal from the camera in an image processing system or a control of monitor TV display.
In the conventional image processing system, the frequency of the system pulse must be an integral multiple of the frequency of the video synchronizing signal, but since the frequency of the video synchronizing signal itself is unstable and fluctuates due to noise contained in the video signal or errors in the video synchronizing signal separation generating circuit itself, there is no quartz oscillator having the frequency perfectly matching with an integral multiple of the frequency of the video synchronizing signal. Furthermore, by resetting the dividing circuit with the video synchronizing signal, the system pulse and the video synchronizing signal are synchronized with each other, but supposing N to be an integer, if a relationship of the video synchronizing signal frequency.times.N=frequency of the system pulse is not established perfectly, the system pulse and the video synchronizing signal are synchronized with each other only right after resetting the dividing circuit, and thereafter the system pulse and the video synchronizing signal differ in frequency and are no longer synchronized, and inputting an accurate video signal and displaying are disabled, and thereby the entire video processing system fails to function.
The invention is devised to solve these problems, and it is an object thereof to present a circuit for generating the video system pulse synchronized perfectly with the video synchronizing signal, by generating a pulse having a frequency of an arbitrary integral multiple of the frequency of the video synchronizing signal deriving from the video synchronizing signal only.